South Korean Researchers Unveil Chameleon Chip That Adjusts Response Speed

Engineers at the Korea Advanced Institute of Science and Technology (KAIST) have developed an adaptive semiconductor device capable of adjusting its internal response speed to process incoming data changing at varied rates.

The hardware breakthrough centres on a programmable dynamic memtransistor (PDM), a device that combines the data-storage capacity of memory with the computational capabilities of a standard transistor.

Led by Chair Professor Shinhyun Choi from the KAIST School of Electrical Engineering and the Graduate School of Semiconductor Technology, the engineering team designed the component to process time-series data without relying on heavy external software operations.

Traditional computing setups and smartphones face significant computational overhead and high power demands when evaluating dynamic, time-varying information because conventional semiconductors feature fixed physical response rates once manufactured.

To bypass these operational bottlenecks, the research team constructed a specialized dual-layer transistor architecture.

Within this dual-layer setup, a dedicated charge storage layer receives and processes incoming electrical data, while an adjacent non-volatile electron trapping layer dynamically regulates the overall device recovery speed across multiple operational levels.

This dynamic configuration allows engineers to tune current recovery times over a fivefold range and adjust frequency response characteristics by more than 10-fold without requiring continuous electrical power supplies.

In experimental trials evaluating intricate time-series data containing mixed fast and slow variables, the new PDM array reduced prediction errors by up to 40 times compared with traditional fixed-response hardware.

Tests conducted on multi-device arrays confirmed that the system matched the analytical precision of complex software algorithms while operating at a fraction of the energy consumption.

The hardware architecture requires no elaborate data preprocessing, allowing direct handling of shifting inputs across edge computing deployments like autonomous equipment, robotic control systems, and field-level environmental monitoring units.

Furthermore, the manufacturing technique aligns with existing complementary metal-oxide-semiconductor (CMOS) fabrication lines, offering a clear path toward commercial mass production.

Professor Choi noted that adjusting hardware characteristics directly at the chip level provides a critical foundation for low-power artificial intelligence, enabling rapid processing across unpredictable operational environments.